1. Field of the Invention
This invention relates to digital signal processing devices such as digital signal processors (DSP), which are applicable to signal processing systems using central processing systems (CPU).
This application is based on Patent Application No. Hei 10-122188 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
Some of the conventional digital signal processing devices are designed based on the so-called xe2x80x9cHarvard Architecturexe2x80x9d. This architecture is suitable for the high speed calculations such as multiplication and is designed to have three memories. That is, two memories are used for storing coefficient data and multiplier data which are input to adders and multipliers and are used for addition and multiplication, while one memory is used for storing DSP instructions. The digital signal processing devices employing the aforementioned Harvard architecture have an advantage that speed of digital signal processing can be increased because both of the coefficient data and multiplier data can be simultaneously set to the adders and multipliers.
However, each of the aforementioned digital signal processors requires address spaces independently for the three memories respectively. For this reason, they have disadvantages that a number of address lines becomes large while an area (or size) of a chip should be enlarged. In other words, the three memories cannot mutually exchange the DSP instructions, coefficient data and multiplier data therebetween. So, even if the memory exclusively used for storing the multiplier data runs out vacant space thereof, it is impossible to use vacant space of the memory exclusively used for storing the coefficient data. So, the conventional digital signal processing devices suffer from a problem that a memory use efficiency is not so good.
It is an object of the invention to provide a digital signal processing device which is capable of improving speed of digital signal processing and memory use efficiency and which is applicable to a signal processing system using a CPU.
According to this invention, a digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor (i.e., DSP), which are connected together using a data bus and an address bus.
The external memory stores multiplier data and coefficient data as well as basic instructions. In the DSP an ALU calculates addresses for accessing the external memory via the address bus. A bus control unit identifies the multiplier data, coefficient data and basic instructions respectively, which are read from the external memory. The DSP performs calculations containing multiplication using the multiplier data and coefficient data. The DSP is controlled in operations in response to a CPU mode and a DSP mode, one of which is selected by decoding the basic instruction(s) identified by the bus control unit. At the CPU mode, the basic instructions of sixteen bits are subjected to coding to produce high-speed instructions of thirty-two bits for controlling the DSP. At the DSP mode, high-speed instructions, which are stored in an internal memory of the DSP, are subjected to consecutive reading and are used for controlling the DSP. Such consecutive reading of the high-speed instructions is started by the basic instruction(s).
Because the digital signal processing device uses the external memory for storing the multiplier data and coefficient data as well as the basic instructions of sixteen bits while using an internal memory for storing the high-speed instructions of thirty-two bits, it is possible to improve the memory use efficiency. In addition, because the high-speed instructions are subjected to consecutive reading at the DSP mode, it is possible to reduce the access time of the high-speed instructions, in other words, it is possible to avoid reduction of the processing speed of the DSP.